Regviz

NXP Semiconductors /LPC43xx /SDMMC /CLKDIV

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CLKDIV

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/NXP Semiconductors/LPC18xx/SDMMC/CLKDIV#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLK_DIVIDER00CLK_DIVIDER10CLK_DIVIDER20CLK_DIVIDER3

Description

Clock Divider Register

Fields

CLK_DIVIDER0

Clock divider-0 value. Clock division is 2n. For example, value of 0 means divide by 20 = 0 (no division, bypass), value of 1 means divide by 21 = 2, value of ff means divide by 2255 = 510, and so on.
CLK_DIVIDER1

Clock divider-1 value. Clock division is 2n. For example, value of 0 means divide by 20 = 0 (no division, bypass), value of 1 means divide by 21 = 2, value of ff means divide by 2255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported.
CLK_DIVIDER2

Clock divider-2 value. Clock division is 2n. For example, value of 0 means divide by 20 = 0 (no division, bypass), value of 1 means divide by 21 = 2, value of ff means divide by 2255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported.
CLK_DIVIDER3

Clock divider-3 value. Clock division is 2n. For example, value of 0 means divide by 20 = 0 (no division, bypass), a value of 1 means divide by 21 = 2, a value of ff means divide by 2255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported. divide by 20 = 0 (no division, bypass), value of 1 means divide by 21 = 2, value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data